A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield during IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
With the scaling down of integrated circuit dimensions, openings, which are etched within the integrated circuit, are reduced in size. The aspect ratio of the opening, which is defined as the ratio of the depth of the opening to the width of the opening, increases with scaling down of integrated circuit dimensions.
The present invention is described with copper metallization for small geometry integrated circuits. However, the present invention may be used with any other conductive material that is amenable for small geometry integrated circuits aside from just the example of copper, as would be apparent to one of ordinary skill in the art from the description herein.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and shorted metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration failure and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
However, copper lines cannot be etched using conventional etching processes as used for aluminum. Thus, copper lines are typically fabricated using a damascene etch process. In such a process, a trench is etched within an insulating layer. That trench is then filled with copper. The surface of the integrated circuit is then polished such that the copper line is contained within the trench.
Referring to FIG. 1, integrated circuits typically include multi-level metallization. A first metal line 102 is contained within a first trench 104 etched in a first trench insulating layer 106. A second metal line 108 is contained within a second trench 110 etched in a second trench insulating layer 112. The first metal line 102 is on a first metallization level on the integrated circuit, and the second metal line 108 is on a second metallization level on the integrated circuit. A via interconnects the metal lines 102 and 108 on the two different metallization levels. A via plug 114 is comprised of a conductive material and is disposed within a via hole 116 etched in a via insulating layer 118. The insulating layers 106, 112, and 118 are comprised of any insulating material such as any form of oxides as is known to one of ordinary skill in the art.
Referring to FIG. 2, if the second trench 110 and the via hole 116 were not filled with a conductive material, a top view of the integrated circuit of FIG. 1 shows the second trench 110 running over the via hole 116. The first metal line 102 is disposed on the bottom of the via hole 116. FIG. 1 is a cross-sectional view of the integrated circuit of FIG. 2 along line AA after the via hole 116 and the second trench 110 have been filled with a conductive material.
In addition, copper is a mid-bandgap impurity in silicon and silicon dioxide. Thus, copper may diffuse easily into these common integrated circuit materials. For example, a copper plug within a via hole may contact the insulating layer surrounding the via hole. Because copper may easily diffuse into the insulating layer, this diffusion may degrade the performance of integrated circuits. Nevertheless, use of copper metallization is desirable for further scaling down integrated circuit dimensions because of the lower bulk resistivity and the higher electromigration tolerance.
Thus, a diffusion barrier layer is deposited between copper and any surrounding insulating layer. The diffusion barrier layer impedes diffusion of copper into the surrounding insulating layer. For example, referring to FIG. 1, a diffusion barrier layer would be disposed on the side walls of the via hole 116 between the via plug 114 and the via insulating layer 118. Such a diffusion barrier layer impedes diffusion of copper from the via plug 114 into the via insulating layer 118.
In the prior art, the diffusion barrier layer is deposited into the via hole 116, and then the via hole 116 is filled with the via plug 114. However, for small geometry metal lines, the via hole 116 may have a relatively high aspect ratio such that depositing a diffusion barrier layer into the via hole 116 is difficult. When the via hole 116 has a relatively high aspect ratio, the diffusion barrier layer may not effectively adhere to the side walls and corners of the via hole 116.
Thus, a method for efficiently forming a via plug having high aspect ratio within an insulating layer is desired with a diffusion barrier layer effectively surrounding the via plug.